OpenEP3C16-C User Manual
Overview
- Basic operation and demo user guide of Waveshare FPGA Altera serial board[1] are in the present document for helping you quick start your FPGA development.
Hardware Design
- This chapter mainly about the basic idea of core-board hardware design. Go with you to witness how a chip evolves to a board.
- There are voltage regulator AMS1117, serial FLASH memory EPCS16, crystal oscillator, JTAG interface, LEDs, buttons, etc., beside main FPGA. Then, how and why do the devices connect together? What are their functions?
Framework of the Circuit
Power Supply Circuit
- Power Supply Circuit is the basic circuit for normal operation. You can find voltage supplies details from the File:Cyclone-IV-Device-Handbook.pdf. Noting that EP3C16 requires 1.0V/1.2V for Internal core supply voltage (VCCINT) and PLL digital power supply (VCCD_PLL), requires 2.5V for PLL analog power supply (VCCA). Then I/O banks power supply VCCO can be connected to 1.2V, 1.5V, 1.8V, 2.5V, 3.0V, 3.3V to supply each area with different voltage standards. So for normal operation, the power supply of the board is designed for converting input voltage 5V to multiple voltages 3.3V, 2.5V, 1.2V. Meanwhile, a PWR LED is connected to 3.3V output, to meet the needs of checking power operation status. The schematic of the circuit:
Pin Name | Description |
---|---|
VCC5 | 5V supply voltage, External Input |
VCC33 | 3.3V voltage, converted from AMS1117-3.3, is generally used to supply the voltage of clock, configure circuit, special features pin high, etc. |
VCC25 | 2.5V voltage, converted from AMS1117-2.5, is generally used to supply the voltage of VCCA. |
VCC12 | 1.2V voltage, converted from AMS1117-1.2, is generally used to supply the voltage of VCCINT, VCC_PLL, etc. |
Clock Circuit
- The best solution of FPGA clock circuit is: A main clock, which is driven by dedicated global clock input(GCLK), controls each timing device of the design. Try to use global clock at any design. The FPGA has dedicated global clock pin, which is connected to each register of the device. The shortest time span of GCLK can supply is used for delay. We use a global clock interface CLK in our design, because it is single clock interface, we consider the use of active crystal clock as an external clock source. A 50MHz crystal oscillator on board is used for supply accurate clock. The schematic of the circuit:
- The best solution of FPGA clock circuit is: A main clock, which is driven by dedicated global clock input(GCLK), controls each timing device of the design. Try to use global clock at any design. The FPGA has dedicated global clock pin, which is connected to each register of the device. The shortest time span of GCLK can supply is used for delay. We use a global clock interface CLK in our design, because it is single clock interface, we consider the use of active crystal clock as an external clock source. A 50MHz crystal oscillator on board is used for supply accurate clock. The schematic of the circuit:
Pin Name | Description |
---|---|
CLK | Clock input |
Reset Circuit
- The Reset Circuit contains RST Reset Circuit and nCONFIG Reconfigure Circuit. RST reset Circuit is a RC reset Circuit with RESET button switch, which is pressed to generate a Reset-signal, active-low. While nCONFIG Reset Circuit is triggered by nCONFIG key. FPGA will be reconfigured without reboot when the nCONFIG key is pressed. The schematic of the circuit:
Pin Name | Description |
---|---|
RESET | Active-low Reset |
nCONFIG | Active-low Reset, FPGA will be reconfigured, as soon as PROG_B pin restores to high level |
Configuration/Programming Interface
- Configuration is also known as loading and download. It is a process of FPGA programming. FPGA reconfigured at each reboot is a feature of SRAM-based FPGA. Within the FPGA, many programmable multiplexers, logic, interconnect nodes and RAM initialization, etc. are controlled by configuration data, which is stored in FPGA RAM.
- The configured data of FPGA can be downloaded to target device with 3 methods, FPGA Active, FPGA Passive and JTAG, according to the role played in Configure Circuit. JTAG is an industry-standard interface. Usually All Altera FPGA can be configured via JTAG commands. Meanwhile, JTAG has more priority than other configuration method. Of course this board provides JTAG interface. The schematic of the circuit:
- User can use dedicated Altera programmer USB Blaster to debug and program. File to be programmed to EPCS should be converted to .jic file by Quartus. That is, Set it as "JTAG Indirect Configuration File" and then uses the JTAG interface to program the EPCS device. See File:Cyclone-IV-Device-Handbook.pdf.
Pin Name | Description |
---|---|
TDI | Test data input. Serial input pin for instructions as well as test and programming data. |
TDO | Test data output. Serial data output pin for instructions as well as test and programming data. |
TMS | Test mode select. Input pin that provides the control signal to determine the transitions of the TAP controller state machine. |
TCK | Test clock input. The clock input to the BST circuitry. |
Configuration Circuit
- An EPCS16, Altera EPCS serial flash devices, is connected to the FPGA for keeping the data without power supplied. EPCS16 is one of advanced Configuration Device, 16Mbit density. It supports high capacity single configuration of FPGA. It also support in-system programming by JTAG interface. The schematic of the circuit:
LED Circuit
- 4 LEDs onboard. Each LED is driven via one of the FPGA pins. When a low level inputs to LED pin, the corresponding LED turns on. The schematic of the circuit:
Extention Board interface
- Series of Open boards designed by Waveshare are based on Core-Extension-Separated idea. On the one hand, users can easily design extension circuit according to their needs, On the other hand, the interfaces of core board and extension board are fully considered about the compatible to other FPGA boards, make update easier.
Basic Operation
Power Up And Download
- Power up CoreEP3C16 with 5V supply. That is, connect corresponding 5V pin and GND pin to a 5V supply by jumper wires. Then the PWR_LED will light up in usual. The onboard JTAG interface is used for programming with dedicated programmer USB Blaster, as shown in the following figure:
- If you use CoreEP3C16 and OpenEP3C16-C together, just connect the core board to the mother board, and plug a 5V adapter directly without any jumper wire. Turn the switch on to power up.
- Run the software Quartus II to download the Verilog and VHDL demo:
General Download Process
- 1. Copy the Nios II processors (Quartus II projects) to your computer, which are located in ".\nios\Quartus II Project".
- 2. Launch Nios II IDE
- 1) Create a new Nios II project.
- 2) Config the Nios processor by specifying the PTF file directory on the "Select Target Hardware" section. The PTF file directory depends on where you placed the Nios II processors in step 1.
- 3) Copy the corresponding c code in ".\nios\Nios II C Code" into the new project.
- 4) Build the new Nios II project.
- 3. Connect the development board to the PC through a download cable.
- 4. Back to the Nios II IDE
- 1) Download the Nios II processor to the FPGA, select"Tools->Quaters II Programmer" to download the sof file.
- 2) Run the Nios II project (right click the makefile, select "Run ->Run As->2 Nios II Hardware", it may takes several minutes). When download completed, the demo code should starts to run automatically.
Quick Start
- All the following demo require power supply. Verilog, VHDL and NIOS are used in the following demos, please download the corresponding one.
- An OpenEP4CE10-C development board is used for demonstration, other Altera boards are similar to it. If there are differences on any example, they will be special explained.
- All the following demo require power supply. Verilog, VHDL and NIOS are used in the following demos, please download the corresponding one.
Light Up LEDs
Language |
Verilog |
VHDL |
Nios II C |
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Sample Program Name |
LED |
LED_hello_world | |
Steps |
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Phenomena |
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JOYSTICK Demo
Language |
Verilog |
VHDL |
Nios II C |
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Sample Program Name |
JOYSTICK | ||
Steps |
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Phenomena |
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8 Push Buttons Demo
Language |
Verilog |
VHDL |
Nios II C |
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Sample Program Name |
8 Push Buttons |
—— | |
Steps |
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Phenomena |
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8 SEG LED Board Demo
Language |
Verilog |
VHDL |
Nios II C |
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Sample Program Name |
8 SEG LED Board |
—— | |
Steps |
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Phenomena |
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4x4 Keypad Demo
Language |
Verilog | VHDL | Nios II C |
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Sample Program Name |
4x4 Keypad | ||
Steps |
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Phenomena |
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DS18B20 Temperature Sensor Demo
Language |
Verilog | VHDL | Nios II C |
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Sample Program Name |
DS18B20 | ||
Steps |
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Phenomena |
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Buzzer Demo
Language |
Verilog |
VHDL |
Nios II C |
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Sample Program Name |
Buzzer/PWM |
—— | |
Steps |
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Phenomena |
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PS/2 Keyboard Demo
Language |
Verilog | VHDL | Nios II C |
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Sample Program Name |
PS2 | ||
Steps |
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Phenomena |
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VGA monitor Demo
Language |
Verilog | VHDL | Nios II C |
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Sample Program Name |
VGA_color | VGA | —— |
Steps |
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Phenomena |
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LCD1602 Demo
Language |
Verilog |
VHDL |
Nios II C |
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Sample Program Name |
LCD1602 |
—— | |
Steps |
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Phenomena |
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LCD12864 Demo
Language |
Verilog | VHDL | Nios II C |
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Sample Program Name |
LCD12864 | —— | —— |
Steps |
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Phenomena |
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LCD32 touch screen Demo
Language |
Verilog | VHDL | Nios II C |
---|---|---|---|
Sample Program Name |
—— | —— | LCD32 |
Steps |
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Phenomena |
should be reset before downloading the demo code each time) |
USB Communication Demo
Language |
Verilog | VHDL | Nios II C |
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Sample Program Name |
—— | USB | —— |
Steps |
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Phenomena |
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Remark |
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SD-Card Demo
Language |
Verilog | VHDL | Nios II C |
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Sample Program Name |
—— | —— | SD-Card |
Steps |
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Phenomena |
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Ethernet Control Demo
Language |
Verilog | VHDL | Nios II C |
---|---|---|---|
Sample Program Name |
—— | —— | ENC28J60 |
Steps |
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Phenomena |
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UART Demo
Language |
Verilog | VHDL | Nios II C |
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Sample Program Name |
UART | ||
Steps |
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Phenomena |
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I2C EEPROM Demo
Language |
Verilog | VHDL | Nios II C |
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Sample Program Name |
AT24CXX | ||
Steps |
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Phenomena |
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Remark |
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AT45DB Demo
Language |
Verilog | VHDL | Nios II C |
---|---|---|---|
Sample Program Name |
—— | —— | AT45DBXX |
Steps |
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Phenomena |
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PCF8563 Demo
Language |
Verilog | VHDL | Nios II C |
---|---|---|---|
Sample Program Name |
—— | —— | PCF8563 |
Steps |
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Phenomena |
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FT245 Demo
Language |
Verilog | VHDL | Nios II C |
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Sample Program Name |
—— | —— | FT245 |
Steps |
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Phenomena |
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