Overview

Open3S500E is an FPGA development board that consists of the mother board DVK600 and the FPGA core board Core3S500E.

Open3S500E supports further expansion with various optional accessory boards for specific application. The modular and open design makes it the ideal for starting application development with XILINX Spartan-3E series FPGA devices.

What's on the mother board

1. FPGA CPLD core board connector: for easily connecting core boards which integrate an FPGA CPLD chip onboard
2. 8I/Os_1 interface, for connecting accessory boards/modules
3. 8I/Os_2 interface, for connecting accessory boards/modules
4. 16I/Os_1 interface, for connecting accessory boards/modules
5. 16I/Os_2 interface, for connecting accessory boards/modules
6. 32I/Os_1 interface, for connecting accessory boards/modules
7. 32I/Os_2 interface, for connecting accessory boards/modules
8. 32I/Os_3 interface, for connecting accessory boards/modules

9. SDRAM interface
   • for connecting SDRAM accessory board
   • also works as FPGA CPLD pins expansion connectors
10. LCD interface, for connecting LCD22, LCD12864, LCD1602
11. ONE-WIRE interface: easily connects to ONE-WIRE devices (TO-92 package), such as temperature sensor (DS18B20), electronic registration number (DS2401), etc.
12. 5V DC jack
13. Joystick: five positions
14. Buzzer
15. Potentiometer: for LCD22 backlight adjustment, or LCD12864, LCD1602 contrast adjustment
16. Power switch
17. Buzzer jumper
18. ONE-WIRE jumper
19. Joystick jumper

The DVK600 supports a wide range of different core boards, therefore, some of the interfaces may be Not-Connected and useless while connecting to certain core board. For instance, while connecting to Core3S500E/CoreEP2C8, the '⑧ 32I/Os_3' is Not-Connected.

What's on the Core3S500E

1. XC3S500E:the XILINX Spartan-3E FPGA device which features:
   • Operating Frequency: 50MHz
   • Operating Voltage: 1.15V～3.3V
   • Package: QFP208
   • I/Os: 116
   • LEs: 500K
   • RAM: 360kb
   • DCMs: 4
   • Debugging/Programming: supports JTAG
2. AMS1117-3.3, 3.3V voltage regulator
3. AMS1117-2.5, 2.5V voltage regulator
4. AMS1117-1.2, 1.2V voltage regulator
5. XCF04S, onboard serial FLASH memory, for storing code
6. Power indicator
7. LEDs
8. FPGA initialization indicator
9. Reset button
10. nCONFIG button: for re-configuring the FPGA chip, the equivalent of power reseting
11. 50M active crystal oscillator
12. JTAG interface: for debugging/programming
13. FPGA pins expander, VCC, GND and all the I/O ports are accessible on expansion connectors for further expansion

Photos

Open3S500E Development Board

Open3S500E Development Board

Open3S500E Development Board back view

Mother Board DVK600

FPGA core board Core3S500E

FPGA core board Core3S500E

Connecting to various peripherals

Connecting to LCD12864

Connecting to LCD1602

Connecting to RS232 Board

Connecting to USB UART Board

Connecting to 8 SEG LED Board

Connecting to 8 Push Buttons

Connecting to 4x4 Keypad

Connecting to EEPROM Board

Multi peripherals connected to one interface

Connecting to DataFlash Board

Connecting to CY7C68013A USB Board

Connecting to VGA PS2 Board

Connecting to any accessory board you need

Note: The Open3S500E does NOT integrate any programming/debugging function, a programmer/debugger is required.

Examples

The Open3S500E FPGA development board comes with various examples codes for the supported peripherals, which give you a quick start to develop your own application.

Debugging/Programming Interface

The Open3S500E FPGA development board integrates JTAG interface for programming/debugging.

Development Resources

• Related software (Xilinx ISE 12 - supports Winxp/Win7, doesn't support Win8)
• Demo code (Verilog, VHDL)
• Schematic (PDF)
• FPGA development documentations

Wiki: www.waveshare.com/wiki/Open3S500E