Core3S500E
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Overview
- This user manual contains schematic and demo of Waveshare Open3S500E[1] development board. It helps you to quick start your development.
Hardware design
- This chapter mainly about the basic idea of the hardware design of Core3S500E Xilinx core board. Go with you to witness how a XC3S500E chip becomes Core3S500E board.
- There are voltage regulator AMS1117, serial FLASH memory XCF04S, crystal oscillator, JTAG interface, LEDs, buttons, etc., beside main FPGA. See product description What's On Board. Then, how and why do the devices connect together? What are their functions?
Power Supply Circuit
- Power Supply Circuit is the basic circuit for Core3S500E's normal operation. You can find voltage supplies details from the datasheet. Noting that XC3S500E requires 2.5V for Internal core supply voltage (VCCINT), requires 2.5V for Auxiliary supply voltage (VCCAUX). Then IO voltage VCCO_0/1/2/3 can be connected to 3.3V, 2.5V, 1.8, 1.5V, or 1.2V to supply each area with different voltage standards. So for normal operation, the power supply of the board is designed for converting input voltage 5V to multiple voltages 3.2V, 2.5V, 1.2V. Meanwhile, a PWR LED is connected to 3.3V output for the needs of checking power operation status. The schematic of the circuit:
- Power Supply Circuit is the basic circuit for Core3S500E's normal operation. You can find voltage supplies details from the datasheet. Noting that XC3S500E requires 2.5V for Internal core supply voltage (VCCINT), requires 2.5V for Auxiliary supply voltage (VCCAUX). Then IO voltage VCCO_0/1/2/3 can be connected to 3.3V, 2.5V, 1.8, 1.5V, or 1.2V to supply each area with different voltage standards. So for normal operation, the power supply of the board is designed for converting input voltage 5V to multiple voltages 3.2V, 2.5V, 1.2V. Meanwhile, a PWR LED is connected to 3.3V output for the needs of checking power operation status. The schematic of the circuit:
| Pin Name | Description |
|---|---|
| 5V | 5V supply voltage, External Input |
| VCC3.3 | 3.3V voltage, converted from AMS1117-3.3, is generally used to supply the voltage of clock, configure circuit, special features pin high, etc. |
| VCC2.5 | 2.5V voltage, converted from AMS1117-2.2, is generally used to supply the voltage of VCCAUT, VCCO_X , etc. |
| VCC1.2 | 1.2V voltage, converted from AMS1117-1.2, is generally used to supply the voltage of VCCINT, VCCO_X , etc. |
Clock Circuit
- The best solution of FPGA clock circuit is: A main clock, which is driven by dedicated global clock input(GCLK), controls each timing device of the design. Try to use global clock at any design. The FPGA has dedicated global clock pin, which is connected to each register of the device. The shortest time span of GCLK can supply is used for delay. We use a global clock interface CLK in our design, because it is single clock interface, we consider the use of active crystal clock as an external clock source. A 50MHz crystal oscillator on board is used for supply accurate clock. The schematic of the circuit:
- The best solution of FPGA clock circuit is: A main clock, which is driven by dedicated global clock input(GCLK), controls each timing device of the design. Try to use global clock at any design. The FPGA has dedicated global clock pin, which is connected to each register of the device. The shortest time span of GCLK can supply is used for delay. We use a global clock interface CLK in our design, because it is single clock interface, we consider the use of active crystal clock as an external clock source. A 50MHz crystal oscillator on board is used for supply accurate clock. The schematic of the circuit:
| Pin Name | Description |
|---|---|
| CLK | Clock input |
Reset Circuit
- The Reset Circuit contains RST Reset Circuit and nCONFIG Reconfigure Circuit. RST reset Circuit is a RC reset Circuit with RESET button switch, which is pressed to generate a Reset-signal, active-low. While nCONFIG Reset Circuit is triggered by nCONFIG key. FPGA will be reconfigured without reboot when the nCONFIG key is pressed. The schematic of the circuit:
- The Reset Circuit contains RST Reset Circuit and nCONFIG Reconfigure Circuit. RST reset Circuit is a RC reset Circuit with RESET button switch, which is pressed to generate a Reset-signal, active-low. While nCONFIG Reset Circuit is triggered by nCONFIG key. FPGA will be reconfigured without reboot when the nCONFIG key is pressed. The schematic of the circuit:
| Pin Name | Description |
|---|---|
| RESET | Active-low Reset |
| PROG_B | Active-low Reset, FPGA will be reconfigured, as soon as PROG_B pin restores to high level |
Configuration/Programming Interface
- Configuration is also known as loading and download. It is a process of FPGA programming. FPGA reconfigured at each reboot is a feature of SRAM-based FPGA. Within the FPGA, many programmable multiplexers, logic, interconnect nodes and RAM initialization, etc. are controlled by configuration data, which is stored in FPGA RAM.
- The configured data of FPGA can be downloaded to target device with 3 methods, FPGA Active, FPGA Passive and JTAG, according to the role played in Configure Circuit. JTAG is an industry-standard interface. Usually All FPGA can be configured via JTAG commands. Meanwhile, JTAG has more priority than other configuration method. Of course this board provides JTAG interface. The schematic of the circuit:
- The configured data of FPGA can be downloaded to target device with 3 methods, FPGA Active, FPGA Passive and JTAG, according to the role played in Configure Circuit. JTAG is an industry-standard interface. Usually All FPGA can be configured via JTAG commands. Meanwhile, JTAG has more priority than other configuration method. Of course this board provides JTAG interface. The schematic of the circuit:
- User can use dedicated programmer Platform Cable USB to debug and program. File to be programmed to XCF02S PROMs should be converted to .msc file by Xilinx ISE.
| Pin Name | Description |
|---|---|
| TDI | Test Data In |
| TDO | Test Data Out |
| TMS | Test Mode Select. This is the JTAG mode signal that establishes appropriate TAP state transitions for target ISP devices. |
| TCK | Test Clock. This is the clock signal for JTAG operations, and should be connected to the TCK pin on all target ISP devices that share the same data stream. |
Configuration Circuit
- A PROM XCF04SA, Platform Flash series of in-system programmable configuration PROM, is connected to the FPGA for keeping the data without power supplied. XCF04S is one of advanced Configuration PROM, 4Mbit density. It supports high capacity single configuration of FPGA. It also support in-system programming by JTAG interface. The schematic of the circuit:
- A PROM XCF04SA, Platform Flash series of in-system programmable configuration PROM, is connected to the FPGA for keeping the data without power supplied. XCF04S is one of advanced Configuration PROM, 4Mbit density. It supports high capacity single configuration of FPGA. It also support in-system programming by JTAG interface. The schematic of the circuit:
LED Circuit
- 4 LEDs onboard. each LED is driven via one of the FPGA pins. When a low level inputs to LED pin, the corresponding LED turns on. The schematic of the circuit:
- 4 LEDs onboard. each LED is driven via one of the FPGA pins. When a low level inputs to LED pin, the corresponding LED turns on. The schematic of the circuit:
Extention Board interface
- Series of Open boards designed by Waveshare are based on Core-Extension-Separated idea. On the one hand, users can easily design extension circuit according to their needs, On the other hand, the interfaces of core board and extension board are fully considered about the compatible to other FPGA boards, make update easier.
Basic operation
Power Up And Download
- Power up Core3S500E with 5V supply. That is, connect corresponding 5V pin and GND pin to a 5V supply by wires. Then the PWR_LED will light up in usual. The onboard JTAG interface is used for programming with dedicated programmer Platform Cable USB, as shown in the following figure:
- Power up Core3S500E with 5V supply. That is, connect corresponding 5V pin and GND pin to a 5V supply by wires. Then the PWR_LED will light up in usual. The onboard JTAG interface is used for programming with dedicated programmer Platform Cable USB, as shown in the following figure:
- Note: A JTAG adapter is needed when you connect Platform Cable USB to the JTAG interface onboard, and please ensure the direction of the arrow on JTAG adapter is direct to the upside of the programmer.
Example quick start
- All the following demos require power supplied. Verilog and VHDL are used in the following demos, please download the corresponding one.
- An open3S500E development board is used for demonstration, Other Xilinx boards are similar to it. If there are differences on any example, they will be special explained.
- All the following demos require power supplied. Verilog and VHDL are used in the following demos, please download the corresponding one.
Test 1, Light up LEDs
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Language |
Verilog |
VHDL |
|---|---|---|
Sample Program Name |
LED | |
Steps |
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Phenomena |
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Test 2, JOYSTICK Test
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Language |
Verilog |
VHDL |
|---|---|---|
Sample Program Name |
JOYSTICK | |
Steps |
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Phenomena |
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Test 3, 8 Push Buttons Test
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Language |
Verilog |
VHDL |
|---|---|---|
Sample Program Name |
8 Push Buttons | |
Steps |
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Phenomena |
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Test 4, 8 SEG LED Board Test
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Language |
Verilog |
VHDL |
|---|---|---|
Sample Program Name |
8 SEG LED Board | |
Steps |
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Phenomena |
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Test 5, 4x4 Keypad Test
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Language |
Verilog |
VHDL |
|---|---|---|
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Sample Program Name |
4x4 Keypad | |
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Steps |
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Phenomena |
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Test 6, DS18B20 Temperature Sensor Test
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Language |
Verilog | |
|---|---|---|
| Sample Program Name | DS18B20 | |
| Steps |
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| Phenomena |
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Test 7, Buzzer Test
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Language |
Verilog |
VHDL |
|---|---|---|
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Sample Program Name |
PWM / Buzzer | |
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Steps |
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Phenomena |
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Test 8, PS/2 Keyboard Test
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Language |
Verilog |
VHDL |
|---|---|---|
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Sample Program Name |
PS2 | |
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Steps |
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Phenomena |
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Test 9, VGA Test
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Language |
Verilog |
VHDL |
|---|---|---|
| Sample Program Name | VGA | |
| Steps |
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| Phenomena |
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Test 10, LCD1602 Test
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Language |
Verilog |
VHDL |
|---|---|---|
| Sample Program Name | LCD1602 | |
| Steps |
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| Phenomena |
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Test 11, LCD12864 Test
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Language |
Verilog |
VHDL |
|---|---|---|
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Sample Program Name |
LCD12864 | |
| Steps |
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| Phenomena |
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Test 12, USB Communication Test
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Language |
VHDL | |
|---|---|---|
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Sample Program Name |
USB | |
| Steps | Connect the pin side of CY7C68013A USB Board to 32I/Os_1 interface, and connect the USB side to PC's USB port. Download the program | |
| Phenomena | Run USB_LED.exe on the PC to control onboard LED. | |
Test 13, UART Serial Test
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Language |
Verilog |
VHDL |
|---|---|---|
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Sample Program Name |
UART | |
| Steps |
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| Phenomena |
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Test 14, I2C EEPROM Test
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Language |
Verilog |
VHDL |
|---|---|---|
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Sample Program Name |
AT24CXX | |
| Steps |
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| Phenomena |
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Test 15, AT45DBTest
| Language | Verilog | |
|---|---|---|
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Sample Program Name |
AT45DBXX_SPI | |
| Steps |
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| Phenomena |
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Test 16, PCF8563 Clock Test
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Language |
Verilog | |
|---|---|---|
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Sample Program Name |
PCF8563 | |
| Steps |
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| Phenomena |
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Test 17, PCF8591 A/D Test
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Language |
Verilog | |
|---|---|---|
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Sample Program Name |
PCF8591 | |
| Steps |
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| Phenomena |
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